The bypass capacitor is mainly used to filter out the AC component of the power supply or input signal to stabilize the voltage and reduce interference.
For example, when the supply voltage is 5V, the bypass capacitor can effectively filter out the AC noise, making the fluctuating voltage (such as the blue waveform) smoother and more stable (such as the pink waveform). Therefore, the bypass capacitor is usually placed close to the power supply to guarantee its best effect.
The decoupling capacitor is mainly used in the power pin of the chip. During the operation of the chip, some unstable waveforms may be produced on the power pin due to the sudden change of current. The role of the decoupling capacitor is to filter out unwanted signal interference at these times, preventing them from feeding back into the power system and affecting the normal operation of the entire circuit.
Formation of peak current:
Peak current formation: In a digital circuit, the current (Ioh) pulled from the power supply at a high level output and the current (Iol) injected at a low level output are usually not the same, and the Iol is usually greater than the Ioh. Take TTL and not gate as an example:
The output voltage is shown in figure (a), the waveform of theoretical power supply current is shown in figure (b), and the actual power supply current is shown in figure (c). As you can see, when the output is converted from a low level to a high level, there is a short and large spike in the power supply current. The waveform of this spike current will vary depending on the type of device used and the capacitance load at the output.
The main causes of the spike current are:
The main reason for the peak current is that the T3 and T4 tubes of the output stage are switched on simultaneously for a short time. In the process of switching from the output low to the high level of the non-gate, the negative jump in the input voltage creates a large reverse drive current in the base loops of T2 and T3. Since the saturation depth of T3 is designed to be greater than that of T2, the reverse drive current will cause T2 to break off from saturation first. After T2 cutoff, its collector potential rises, resulting in T4 conduction. However, at this time, T3 is not yet saturated, so in a very short time, T3 and T4 will be switched on at the same time, generating a large ic4 current, forming a peak current. The R4 in the figure is designed to limit this spike.
Decoupling capacitors are similar to batteries in that they avoid voltage drops due to sudden current changes and are equivalent to filtering out ripples. The specific capacity value can be calculated according to the current size, the expected ripple amplitude and the action time. If the capacitance value is too large, the suppression effect on high-frequency noise is limited. The bypass capacitor is specially designed for high-frequency noise, using the frequency impedance characteristics of the capacitor to provide a low impedance leakage channel. The high-frequency bypass capacitance is usually small, with a typical value of 0.1uF or 0.01uF; The low-frequency bypass capacitance is larger, usually 10uF or more, depending on the distribution parameters of the circuit and the change in the drive current.
Bypass capacitance
The bypass capacitor is used to filter out high-frequency noise from input signals to eliminate high-frequency interference. Its core role is to provide a shunt path for AC signals, helping to eliminate unwanted energy that enters sensitive areas of the circuit. As a high-frequency bypass device, the bypass capacitor can also reduce the need for transient current in the power module.
Common bypass capacitor materials are aluminum electrolytic capacitors and tantalum capacitors, and the specific capacitor value is usually determined by the transient current requirements on the PCB, usually in the range of 10µF to 470µF.
Decoupling capacitance
decoupling capacitor (also known as decoupling capacitor), the main role is to filter the interference signal output on the chip power pin. It plays two key roles between the integrated circuit power supply and ground: on the one hand, it provides stable energy storage for the circuit, and on the other hand, it guides it to ground (GND) by bypassing the high-frequency noise generated by the device.
In the digital circuit, when the circuit state changes, the power line often produces a large peak current, forming a transient noise, which may affect the normal operation of the preceding circuit. This situation is called coupling. For devices that are sensitive to noise and have sharp current changes when they are turned off, especially memory devices such as ROM and RAM, decoupling capacitors should be connected between their power lines (Vcc) and ground lines (GND) to suppress these noise disturbances.
The decoupling capacitance value commonly used in digital circuits is 0.1µF. With a distributed inductance of about 5µH, this combination resonates around a frequency of about 7MHz, effectively removing noise below 10MHz, but has little effect on noise above 40MHz. For high-frequency noise, decoupling capacitors of 1µF or 10µF work better because their parallel resonant frequencies are usually higher than 20MHz.
In general, every 10 or so pieces of integrated circuit should add a storage capacitor of about 10µF to help cope with current changes in the circuit. Electrolytic capacitors should be avoided as much as possible because their winding structure behaves as inductors at high frequencies, and tantalum capacitors or polycarbonate capacitors are recommended. When selecting decoupling capacitors, you can refer to the empirical formula: C = 1/F, for example, select 0.1µF capacitance for 10MHz noise and 0.01µF capacitance for 100MHz noise.
Case study:
Buffer circuits with and without decoupling (measurement results)
We compare the buffer circuits with and without decoupling capacitors (C1 and C2) for driving R-C loads respectively. When the decoupling capacitor is not used, a high frequency (3.8MHz) oscillation occurs in the output signal. Amplifiers that lack decoupling capacitors often exhibit various abnormal problems such as poor stability, poor transient response, and failure at startup.
Current with and without coupling
The inductance of the power line will limit the supply of transient current. The decoupling capacitor is placed close to the device, so the inductance in the current path is very small. In the transient process, decoupling capacitors can provide a large amount of current to the device in a very short time. Without decoupling capacitors, the device will not be able to provide the required transient current, causing the amplifier’s internal node voltage to drop, a phenomenon commonly referred to as “interference.” Due to the lack of decoupling capacitance, internal power supply interference can cause the device to fail to work properly because the internal nodes fail to obtain the correct bias voltage, affecting the continuous operation of the circuit.
Comparison of good and bad PCB surface layout
In addition to using decoupling capacitors, ensure that the connection between the decoupling capacitor, power supply, and ground is as short as possible and has a low impedance. We compared a good decoupling layout with a bad layout and found that a good layout can significantly improve circuit performance. The decoupling path should be as short as possible, and the use of through holes should be avoided, because through holes will increase inductance and affect the decoupling effect.
Most product manuals recommend an appropriate value for decoupling capacitance, and if not explicitly stated, a capacitor of 0.1µF can usually be used as the default choice.
The decoupling capacitor is placed in the PCB layout
When installing a decoupling capacitor, the first thing to consider is the installation distance. A capacitor with a smaller capacity has the highest resonant frequency, so it has the smallest decoupling radius and should be placed closest to the chip. Capacitors with a larger capacity can be placed a little further away, while capacitors with the largest capacity can be placed further out. However, all capacitors that decouple the chip should be as close to the chip as possible to ensure the best decoupling effect.
Figure 1 below shows an example of capacitor placement, where capacitance values roughly follow a 10-fold hierarchy.
When placing decoupling capacitors, it is also necessary to pay attention to the uniform distribution of capacitors. The capacitors of each capacity level should be evenly distributed around the chip. This is because the chip is usually designed with the arrangement of power and ground pins in mind, often distributed on the four sides of the chip. Therefore, voltage disturbances will be generated in all directions of the chip, and the decoupling capacitor should also cover the entire chip region evenly to effectively suppress these disturbances.
If all the 680pF capacitors are concentrated on one side of the chip, due to the limitation of the decoupling radius, the voltage disturbance on the other side of the chip may not be effectively decoupled, thus affecting the overall performance of the circuit.
Installation of capacitance
When installing capacitors, pay attention to the connection mode to reduce parasitic inductance. The general operation is to pull out a small section of lead wire in the capacitor pad, and then connect to the power plane through the hole, and the ground end is also operated in a similar way. The current circuit of the capacitor is as follows: power plane -> Hole -> Lead wire -> Pad -> Capacitor -> Pad -> Lead wire -> Hole -> Ground plane. Figure 2 shows the current return path directly.
The first method: a long lead wire is drawn from the pad and then connected to the hole. This method introduces a large number of parasitic inductors, which is the least recommended installation method and should be avoided as much as possible.
The second method: drilling holes near the two ends of the pad, the current path is short, and the parasitic inductance is relatively small, which is an acceptable scheme.
The third method: drilling holes on the side of the pad, which further reduces the loop area, so that the parasitic inductance is smaller than the second method, and is a better installation method.
The fourth method: holes are drilled on both sides of the pad, and each end of the capacitor is connected to the power plane and the ground plane through parallel holes. The parasitic inductance of this method is smaller than that of the third, and it is recommended to be preferred if space allows.
The fifth method: directly punch holes on the pad, the parasitic inductance is minimal, but there may be problems in the welding process, whether to use this method depends on the processing technology and equipment capacity.
The third and fourth methods are recommended.
When designing a PCB, one point needs to be emphasized: although some engineers may have multiple capacitors share a single hole in order to save space, this practice should be avoided as much as possible. The best practice is to optimize the capacitor combination design to minimize the number of capacitors.
In addition, the width of the printed wire is inversely proportional to the inductance. Therefore, the lead line from the pad to the hole should be as wide as possible, if conditions permit, the width is best the same as the pad. Even capacitors in the 0402 package can use 20mil wide leads. This design can effectively reduce parasitic inductance. The installation diagram of the lead wire and through hole is shown in Figure 4, which shows the precautions of various sizes.
